[SOLVED] MIPSCMPUT 229 (Winter 2017) Homework #1

CMPUT 229 (Winter 2017) Homework #1

Question 1: (5 points)
Consider that a processor architecture ToyProc, which was initially designed as big- endian, is changed to use little-endian byte ordering. Assuming the subset of the MIPS ISA that you are familiar with, and assuming a memory with a word-level interface, give examples of instructions whose operations will be affected by such a change in endianness.

Question 2: (5 points)
Write the C code that best corresponds to the following MIPS assembly code. Assume that registers $s1, $s2, and $s3 store the values of 32-bit integers x, y, and z.

 L1: beq $s1, $zero, L2 addu $s1, $s1, $s2 addu $s1, $s1, $s3

L2:

Question 3: (15 points)
For this question, assume that:

p, q, i, j are 32-bit integers whose values are stored in $s0, $s1, $s2, and $s3, respectively.

A and B are arrays of integers.

r is a pointer declared as int *r.

r, the base address of array A, and the base address of array B are all in the stack frame of the current function, as shown below

For each of the C statements below, give the translation into MIPS. Do not use pseudo- instructions in your code. Clearly label which MIPS instructions are for which statement.

a. (5 points) q = *r
b. (5 points) B[i] = A[j]

c. (5 points) p = q + A[B[j]] Question 4: (15 points)

Write the assembly code to implement the following C function:

 int selector(int array[], int i) {return array[array[i]];

}

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CMPUT 229 (Winter 2017) Homework #1 Instructor: Karim Ali

Remember that the first parameter of a function is passed to the function in register $a0 and the second parameter is passed in register $a1.

Question 5: (25 points)
You have been hired by Proyota, a manufacturer of embedded processors for cars. A new 8-bit processor is being designed and you need to help answer some questions about the processor. This processor has eight 8-bit registers named R0, R1, , R7, and also operates with an 8-bit word. Answer the following questions:

1. (10 points) In the table below, indicate the values, in the specified forms, that can be stored in an 8-bit register.

   Description Binary Hexadecimal Decimal

   Max unsigned integer
   Max 2s complement integer Min 2s complement integer

2. (15 points) For this part of the question, assume the following:
   The format for arithmetic instructions in this processor is as follows:

   add Ra,Rb,Rc # Ra<Rb+Rc sub Ra,Rb,Rc # Ra<Rb-Rc

   The following values (given in binary) are stored in registers: R1 = 0100 0011,
   R2 = 0100 0000, and
   R3 = 0100 0001.

   What is the result, expressed in decimal, produced by the following sequence of instructions? Is it correct? If not, why not? If the code does not produce the expected result, is there a way to rewrite it to produce correct result? If yes, write the code that performs the correct operation.

add sub

In the table below, indicate how many load word (lw) and how many store word (sw) instructions are necessary to execute each of the C statements.

R4, R2, R3R5, R1, R4

(15 points)
Assume that x, y, i, j are 32-bit integers, and that their values are stored in $s0, $s1, $s2 and $s3, respectively. Assume that A and B are vectors of integers, and that the base address of A is stored in $s4 and the base address of B is stored in $s5.

Question 6:

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CMPUT 229 (Winter 2017) Homework #1 Instructor: Karim Ali

C statement

x=y*y
A[i] = x + y
x = A[i] + A[j] B[i] = A[j]
x = y + A[B[j]] A[B[j]] = x + y

load words (lw)

store words (sw)

Question 7: (20 points)
You are participating in the Computing Science Industrial Internship Program, and your placement is with Tiny Inc., a company that produces TinyProc a new processor de- veloped for the automobile industry. All instructions in TinyProc have 16 bits. TinyProc also works with 16-bit addresses. The format of a branch instruction in TinyProc is as shown below:

15 1312 109 76 0

Where rs and rt specify the source and target registers for the branch instruction, respectively. The address of the target of a branch instruction is computed using the same mechanism used in the MIPS processor, but the increment of the PC and the shift left have to be adjusted for a 16-bit address machine: first the Program Counter (PC) is incremented by two, then the bitfield address of the branch instruc- tion is shifted left by one, sign-extended to sixteen bits, and added to the incremented PC. Based on this information, answer the following questions.

1. (5 points) What is the binary representation of the address field of a branch in- struction that results in the largest jump backward and on the largest jump forward in TinyProc?
2. (5 points) The range of a branch instruction is the address distance between the target of a branch instruction and the branch instruction itself. For example if a branch instruction is at the address 0x0010 and the target is at address is at 0x0020, then the range of this branch instruction is 0x0010 = 1610. What is the maximum range of a branch instruction, expressed as a decimal number in TinyProc?
3. (5 points) How many registers does TinyProc have?
4. (5 points) The instruction beq $0, $1, SKIP branches to the instruction at the label SKIP if the value in register $0 and in register $1 are the same. In TinyProc, the Opcode for a beq instruction is 010. Assume that this instruction is at ad- dress 0xFC00, and that the label SKIP is at address 0xFB82. What is the binary representation of this instruction expressed in Hexadecimal?

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