Utilizing the ALU in Lab2 to implement a simple single cycle CPU. CPU is the most important unit in computer system. Reading the document carefully and do the Lab, you will have elementary knowledge of CPU.
2. Demands
- Please use iverilog
- Simple_Single_CPU.v, Adder.v, ALU.v, ALU_Ctrl.v, Decoder.v,
Instr_Memory.v, Mux2to1.v, Mux3to1.v, Program_Counter.v, Reg_File.v, Shifter.v, Sign_Extend.v, Zero_Filled.v, and TestBench.v are supplied. Please use these modules to accomplish the design of your CPU and dont change the file name.
Instruction set: the following instructions have to running in your designed CPU (80pts.)
| Instruction | Example | Meaning | Op field | Shamt | Function field |
| ADD | add r1,r2,r3 | r1=r2+r3 | 6b000000 | X | 6b010011 |
| SUB | sub r1,r2,r3 | r1=r2-r3 | 6b000000 | X | 6b010001 |
| AND | and r1,r2,r3 | r1=r2&r3 | 6b000000 | X | 6b010100 |
| OR | or r1,r2,r3 | r1=r2|r3 | 6b000000 | X | 6b010110 |
| NOR | nor r1,r2,r3 | r1=~(r2|r3) | 6b000000 | X | 6b010101 |
| SLT | slt r1,r2,r3 | if(r2<r3) r1=1 else r1=0 | 6b000000 | X | 6b110000 |
| SLL | sll rd,rt,5 | rd=rt<<5 | 6b000000 | 5 | 6b000000 |
| SRL | srl rd,rt,5 | rd=rt>>5 | 6b000000 | 5 | 6b000010 |
| ADDI | addi r1,r2,10 | r1=r2+10 | 6b001000 | X | X |
Shifter
The block diagram of the shifter to be implemented is shown:
Shift.v contains the following inputs and outputs:
- sftSrc: A 32-bit input data, is the source data of the shifter.
- leftRight: A 1-bit input control signal. When it is set to 1, the shifter perform logical left shift; else, does logical right shift.
- shamt: A 5-bit input data, represents the number of bit positions to be shifted.
- result: A 32-bit output data, which represents the shifting result of the shifter.
SRL Rd, Rt, shamt (Rs is ignored for SRL)
Shift register Rt right by the distance indicated by immediate shamt
4. Bonus
Implement SLLV (Shift left logical variable) and SRLV (Shift right logical variable) instructions. You can add new module or control signal in this advanced design.
| Instruction | Example | Meaning | Op field | Shamt | Function field |
| SLLV | sllv rd,rt,rs | rd=rt<<rs | 6b000000 | 5 | 6b000110 |
| SRLV | srlv rd,rt,rs | rd=rt>>rs | 6b000000 | 5 | 6b000100 |
SRLV Rd, Rt, Rs
Shift register Rt right by the distance indicated by the register Rs
5. Test Bench
In Lab3, three test data (binary code), stored in CO_P3_test_data1.txt ~
CO_P3_test_data3.txt, are provided. The default test data is the first one. If you would like to use second test data, modify line 75 in the file TestBench.v as follows: $readmemb(CO_P3_test_data1.txt, cpu.IM.Instr_Mem);
The Assembly codes of the test data are given as follows:
| CO_P3_test_data1.txt | CO_P3_test_data2.txt | CO_P3_test_data3.txt |
| addi r1 r0 10 #r1 = 10 addi r2 r0 4 #r2 = 4 slt r3 r1 r2 #r3 = 0 add r4 r1 r2 #r4 =14 sub r5 r1 r2 #r5 = 6 nor r5 r5 r0 #r5 = -7 | addi r6 r0 3 #r6 = 3 addi r7 r0 14 #r7 = 14 and r8 r6 r7 #r8 = 2 or r9 r6 r7 #r9 = 15 sll r10 r9 3 #r10 = 120 | addi r1 r0 -5 #r1 = -5 addi r2 r0 5 #r2 = 5 slt r3 r1 r2 #r3 = 1 slt r4 r2 r1 #r5 = 0 add r5 r1 r2 #r5 = 0 sub r6 r1 r2 #r6 = -10 |
After the simulation of TestBench, you will get the file CO_P3_result.txt. You can verify the result. If your design passes the test data, the following words would show in the Transcript windows.
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