[Solved] CSC21100 Project 2

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Note: Both project report and the source codes need to be submitted to Blackboard by the end of the due day.

In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) to create a project and complete the following tasks.

Please read the instructions carefully. Failing to follow the instructions would lead to significant point deductions.

Task 1: Inhibit gate (5 points)

Implement an inhibit gate using the source code in Table 5-13.

Note: Please do not just copy & paste the codes into your VHDL source file. The purpose is to make sure you pay attention to all the details in the code. So please type in the codes and add your own comments.

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Use the test-bench program below and run simulations to validate your design.

Deliverables

Requirement(s):

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(1) You must follow the structural design method.(2) You must follow the submission guidelines.Note: no points will be given if any of the requirements are not satisfied.

Rubric (Report)

1. 1.1 Use your own language to describe the function of the component to be implemented in VHDL. (1 points)
2. 1.2 Include your VHDL entity declaration(s) and architecture definition(s). (1 points)
3. 1.3 Show simulation results (e.g. the waveforms). Explain the outcome of each test case. (1 points)

Rubric (Source Code)

1.4 Can compile without any errors. (1 points)1.5 Can run simulations without any errors. (1 points)

Task 2: Prime-number detector (7 points)

Implement a prime number detector according to the source codes in Table 5-30.

Note: Please do not just copy & paste the codes into your VHDL source file. The purpose is to make sure you pay attention to all the details in the code. So please type in the codes and add your own comments.

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Use the test-bench program below and run simulations to validate your design.

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Deliverable(s):

Requirement(s)

(1) You must follow the structural design method.

(2) You must follow the submission guidelines.

Note: no points will be given if any of the requirements are not satisfied.

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Rubric (Report)

1. 2.1 Include your VHDL entity declaration(s) and architecture definition(s). (1 points)
2. 2.2 Show simulation results (e.g. the waveforms). Explain the outcome of each test case. (4 points)

Rubric (Source Code)

2.3 Can compile without any errors. (1 points)2.4 Canrunsimulationswithoutanyerrors.(1points)

Task 3: Excess-3 code detector (8 points)

In the homework assignment, you are asked to design an excess-3 code detector using a two-level NAND-NAND circuit (i.e. only NAND and NOT gates). Please write a VHDL program to implement the circuit using structural design. Make sure you use the entity declaration provided below. No points would be given if failed to follow it.

Use the test-bench program below and run simulations to validate your design.

Deliverables:

Requirement(s):

(1) You must follow the structural design method.(2) You must follow the submission guidelines.Note: no points will be given if any of the requirements are not satisfied.

Rubric (Report)

1. 3.1 Draw a circuit diagram of the module to show the design. (1 point)
2. 3.2 Include your VHDL entity declaration(s), architecture definition(s) and thetestbench program. (1 point)
3. 3.3 Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (4 points)