[Solved] CS301 Assignment 12

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Q 1) A processor has a baseline IPC of 0.8 for a certain program. 30% of the programs instructions are memory operations. It has two levels of caches.The L1 instruction cache has a hit rate of 100%, and hit time of 1 cycle (part of the baseline IPC computation). The L1 data cache miss rate is 5% and the L2 miss rate is 50% for the given program. The L1 data cache hit time is 1 cycle (part of the baseline IPC computation), and the L2 hit time is 10 cycles. The L2 miss penalty is 100 cycles.