Provide answers to the following questions:

1. What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial.
2. Design a fourbit shift left register with parallel load using D flipflops and gates. There are two control inputs: shift and load. When shift = 1, the content of the register is shifted by one position. New data are transferred into the register when load = 1 and shift = 0. If both control inputs are equal to 0, the content of the register does not change. Briefly describe your design and draw the circuit diagram.
3. Design a serial 2s complementer with a shift register, a flipflop and gates. The binary number is shifted out from one side and its 2s complement shifted into the other side of the shift register. Provide the state diagram and draw the circuit diagram.

Hint: 2s complement of a number can be obtained by keeping the least significant bits as such until the first 1, and then complementing all bits

eg: 001010 110110

4. List the all unused states in a 4-bit switchtail ring counter show in the figure below. Determine the next state for each of these states and show that, if the counter finds itself in an invalid state, it does not return to a valid state. Modify the circuit to avoid this. Show that your modified counter produces the same sequence of states and that the circuit reaches a valid state from any one of the unused states.

PART 2: DIGITAL DESIGN LAB

INTRODUCTION

In this lab, you are required to use Vivado 2017.4 and Minisys/EGO1 Practice platform (Xilinx FPGA chip Artix 7 inside) to design a Sequential circuit and test it.

PREAMBLE

Before working on the course-work itself, you should master the following material.

1. CH6-Registers and Counters-SUSTC.ppt in Sakai site.
2. Digital design lab12.pdf, Digital design lab13.pdf, Digital design lab14.pdf in Sakai site.
3. Verilog: http://www.verilog.com

EXERCISE SPECIFICATION

TASK1:

Use two 74194 shift register to implement a 8-bit serial-parallel converter. Write a circuit to realize this function and test.

• Do the design (Using structure design is suggested).
• Write testbench to verify the function of your design.
• Create the constraint file.
• Do the synthetic and implementation, generate the bitstream file and program the device, then test on the Minisys / EGO1 develop board.

TASK2:

Using JK flipflops, design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6.

• Do the design in Verilog.
• Write testbench to verify the function of your design.
• Create the constraint file
• Do the synthetic and implementation, generate the bitstream file and program the device, then test on Minisys /EGO1 the develop board