Implement a Cache that meets the specifications below.

Cache Specifications

Inputs

All of the inputs will only be valid during the SINGLE clock cycle that your Cache says it is Ready. This means that you will have to save your inputs if you need them beyond that first clock cycle.

The only exception to this is LineFromMem. It will be valid as long as you say you want to read from memory. If you arent reading from memory LineFromMem will be EEE and Red (an Error). Dont worry about this. It is normal behavior. As soon as your request to read from memory it will be the value at MemAddress.

Outputs

Why is MemAddress 8 bits instead of 10?

Our Memory is going to be Block Addressable instead of Byte Addressable. This means that each block has an address instead of each byte. This enables you to read a block from/write a block to memory in a single clock cycle which should help simplify your design a little. It should be pretty easy to figure out which bits to drop to form MemAddress. Hint: it is bits that help you pick out the byte within a block.

When are outputs checked?

• DidContain: At the end of every operation once your circuit becomes Ready.
• ByteRead: At the end of a read operation once your circuit becomes Ready.
• MemRead: Whenever you read from memory it increments the MissCounter.

Timing Restrictions

Your circuit must be able to complete a Read/Write request within 10 clock cycles. If you take longer than 10 clock cycles the tester will automatically advance to the next case. This will cause your Cache to start to desync from the tester and so will get everything wrong if you are taking too long. You can certainly finish in less than 10 clock cycles, I only took 7 but Ive seen students get as low as 2.

Testing

1. Open the grading circuit
2. Click on the Cache folder and select reload library
   1. Double-check that your updates are visible inside of the grader. If your changes dont show up, close your solution circuit and try reloading again. If the changes still fail to show up, close the grader and reopen it and then reload the library.
3. Open the subcircuit named CheckerCirc and
   1. Right-click the ROM inside of it
   2. Select Load Image
   3. Select one of the provided files that ends in _sol.txt.
      1. Eample: seq_read1_seq_mem_sol.txt
4. Open the subcircuit named InputGeneratorCirc and
   1. Right-click the ROM inside of it
   2. Select Load Image
   3. Select the corresponding input file that matches with the solution file. This will be the file that shares its name with the first part of the solution file.
      1. Example: seq_read1.txt
5. Go back to the main subcircuit
   1. Right-click the RAM
   2. Select Load Image
   3. Select the corresponding memory file that matches with the solution file. This will be the file that shares its name with the second part of the solution file.
      1. Example: seq_mem.txt

Anytime your reset a test case you must RELOAD the RAM! The RAM is the only one that has to be reloaded. The ROMs will maintain the last value you put in them.

At the bottom of the the main circuit you will find probes that show your circuits inputs, outputs, answers, how many reads you got correct, how many times you said you hit, and how many misses(memory reads) you had. This is a good place to look when you are debugging to get a high level overview of what your cache is doing.

If you open the solution files in a text editor you will find what the correct values for all of the stats should be for that test case.

Testing Order

I recommend running the test cases in the following order

1. seq_read1_seq_mem_sol.txt
2. seq_write1_seq_mem_sol.txt
3. set1_targeted_read_seq_mem_sol.txt
4. set0_targeted_write_seq_mem_sol.txt
5. random0_seq_mem_sol.txt
6. final_test_rand_mem_mem_sol.txt.

User Created Tests

If you want to make your own test, you can use cache_test_maker.py to create your own tests. It should be fairly easy to follow the documentation inside if you feel like using it.